Fabricating a semiconductor device, such as a transistor, upon a substrate necessarily leads to occupation of a certain surface area of the substrate by the footprint of the device. Often, the available surface area of a given substrate is limited, and maximizing the use of the substrate requires maximizing the density of devices fabricated on the substrate. Minimizing the dimensions of components of a device, such as a transistor, accommodates minimizing the overall footprint of the device and maximizing of the device density. This accommodates formation of a greater number of devices on a given substrate.
Transistors are often constructed upon the primary surface of the substrate. The primary surface is generally the uppermost, exterior surface of the substrate. The primary surface of the substrate is considered to define a horizontal plane and direction.
Field effect transistor (“FET”) structures, which include a channel region between a pair of source/drain regions and a gate configured to electrically connect the source/drain regions to one another through the channel region, can be divided amongst two broad categories based on the orientations of the channel regions relative to the primary surface of the substrate. Transistor structures that have channel regions that are primarily parallel to the primary surface of the substrate are referred to as planar FET structures, and those having channel regions that are generally perpendicular to the primary surface of the substrate are referred to as vertical FET (“VFET”) transistor structures. Because current flow between the source and drain regions of a transistor device occurs through the channel region, planar FET devices can be distinguished from VFET devices based upon both the direction of current flow as well as on the general orientation of the channel region. VFET devices are devices in which the current flow between the source and drain regions of the device is primarily substantially orthogonal to the primary surface of the substrate. Planar FET devices are devices in which the current flow between source and drain regions is primarily parallel to the primary surface of the substrate.
A VFET device includes a vertical, so-called “mesa,” also referred to in the art as a so-called “fin,” that extends upward from the underlying substrate. This mesa forms part of the transistor body. Generally, a source region and a drain region are located at the ends of the mesa while one or more gates are located on one or more surfaces of the mesa or fin. Upon activation, current flows through the channel region within the mesa.
VFETs are generally thinner in width (i.e., in the dimension in a plane parallel to the horizontal plane defined by the primary surface of the substrate) than planar FETs. Therefore, vertical transistors are conducive to accommodating increased device packing density and are conducive for inclusion within a cross-point memory array. In such an array, multiple VFETs are ordered in stacked rows and columns. However, even with this arrangement, the packing density is at least partially limited by the minimal dimensions of the components of the vertical transistor, including the gate and channel components.
Scaling or otherwise reducing the dimensions of transistor components depends, at least in part, on the limitations of conventional semiconductor fabrication techniques, physical limitations of materials used in the fabrication, and minimal properties required for fabricating an operational device. For example, to form a typical gate metal having the properties to achieve the necessary level of low electrical resistance, a gate thickness of greater than 5 nanometers is generally required. Using a gate metal of 5 nm thickness in a VFET device having a surround gate, the total width of the device must take into account twice the width of the gate material. Therefore, a typical VFET surround gate will have at least 10 nanometers of the VFET device's width consumed by the gate conductor.